Description
The SN65LVDS324 is a SubLVDS deserializer that recovers words, detects sync codes, multiplies the input DDR clock by a ratio, and outputs parallel CMOS 1.8V data on the rising clock edge.
Features
- 1.
- 23 Bridges the Interface Between Video Image Sensors and Processors.
- Receives Aptina HiSPi™, Panasonic LVDS, or Sony LVDS Parallel; Outputs 1.8V CMOS with 10/12/14/16 Bits at 18.5MHz to 162MHz.
- SubLVDS Inputs Support Up To 648Mbps.
- Integrated 100Ω Differential Input Termination.
- Test Image Generation Feature.
- Compatible with TI OMAP™ and DaVinci™
Including DM385, DM8127, DM36x, and DMVA.
- Low Power 1.8V CMOS Process.
- Confi.
SN65LVDS324 Datasheet
